A capacitive accelerometer is an accelerometer device which measures accelerations (on a surface) using capacitive sensing techniques. It can sense and record acceleration on equipment or devices and converts this acceleration into electrical currents or voltages. Capacitive accelerometers are also sometimes referred to as vibration sensors. They comprise a capacitive micro-electro-mechanical system (MEMS) element operating as a capacitive accelerometer sensor connected to an electronic circuit, referred to also as an interface circuit. When supplied by the electronic circuit, the MEMS element converts the resulting force due to its acceleration into an electrical signal, which in turns is amplified by the electronic circuit, and converted into a useful signal for a given application (for example a digital representation of the acceleration). In capacitive MEMS accelerometers, a change of the MEMS capacitance in presence of the acceleration generates the electrical signal. Capacitive accelerometers are widely implemented in computational and commercial applications, such as airbag deployment sensors in automobiles, human computer interaction devices and smartphones.
The circuits shown in FIGS. 1a and 1b illustrate one example of a capacitive accelerometer system or device 1, referred to simply as a capacitive accelerometer or accelerometer. The accelerometer comprises a capacitive accelerometer sensor 3 and an analogue frontend interface circuit 5 connected to the capacitive accelerometer sensor 3. The sensor in this example comprises two capacitors, namely a first capacitor C1 with a first capacitance c1 and a second capacitor C2 with a second capacitance c2. The first and second capacitors C1, C2 have one common mobile electrode, which is arranged to be displaced when the sensor 3 is subject to an acceleration or deceleration. This displacement generates a capacitance difference between c1 and c2, which can then be detected by the interface circuit 5.
The operation of the interface circuit can be divided into three main operational phases: an auto-zero (AZ) phase, a charge transfer (XFER) phase and an analogue-to-digital conversion phase. FIG. 1a illustrates the circuit configuration during the AZ phase, while FIG. 1b illustrates the circuit configuration during the XFER phase. The analogue-to-digital conversion phase may be further divided into two sub-phases, namely an input tracking phase and a successive approximation register (SAR) convergence phase as explained better in connection with FIG. 2. The charges may be collected from the mobile electrode of the capacitive accelerometer sensor 3 by applying two successive phases (i.e. first and second phases defining a charge transfer period or duration) of each of the two voltage polarities, namely the AZ and XFER phases. During the AZ phase, a first amplifier 7 of the interface circuit 5 is reset. A positive input node of the amplifier is connected to a voltage source VCM1, which in this example supplies a voltage referred to as common mode voltage Vcm, while a negative input node of the first amplifier 7 is connected to the sensor 3. During the XFER phase, the charges are transferred to the first amplifier 7, which transforms these charges to an output voltage value Vout at an amplifier output node Aout. As can be seen in FIGS. 1a and 1b, the first capacitor C1 is connected to a second voltage source 12, while the second capacitor C2 is connected to a third voltage source 13. These two voltage sources 12, 13 may be programmable or they may have the output of supply voltage VDD or VSS. As shown in FIG. 1a, during the AZ phase, a switch S11 is closed, and the first capacitor C1 is connected to the second voltage source 12 now supplying a positive supply voltage VDD, while the second capacitor C2 is connected to the third voltage source now set to 0 V, ie the third voltage source 13 is now grounded. As can be seen in FIG. 1b, during the XFER phase, the switch S11 is first opened, and the second voltage source 12 is set to 0 V, while the third voltage source 13 now supplies the positive supply voltage VDD. At the end of the XFER phase, the output voltage at the amplifier output node Aout isVout=VDD·(c1−c2)/cf,where cf is the capacitance of a feedback capacitor Cf.
The output voltage value Vout at the node Aout can be digitalised by an analogue-to-digital converter (ADC) 9. It is well known that an SAR ADC is a favoured candidate for a low power design with moderate resolution. One single-ended implementation of the ADC 9 based on a charge redistribution method is shown in FIG. 2. During the input tracking phase, switches S12 and S22 are closed, while switches S32 and S42 are open. The switch S32 is connected to a voltage source VDD, which supplies the positive supply voltage VDD, while the switch S42 is connected to a voltage source VSS, which is set to 0 V. The input voltage Vin at the node Aout is tracked by a capacitor array Cdac, where Vin=Vout. A second amplifier 11 is used as an amplifier during input-tracking phase. During the SAR convergence phase, the switches S12 and S22 are open, while the switches S32 and S42 are controlled by an SAR algorithm, i.e. a binary searching algorithm. The second amplifier 11 is used as a comparator during this phase only. The positive input node is connected to a voltage source VCM2 for supplying the common mode voltage Vcm. The input voltage value Vin is digitised as followsDout=Vin/VDD, where Dout is a quantised fractional value.
Since VDD is also used as the reference voltage for the ADC 9 in the accelerometer 1, the digitised acceleration can be expressed asDout=(c1−c2)/cf,where Dout is a quantized fractional number.
For the accelerometer 1, it is also required to be able to tune the gain, which is defined as:Gain=Dout/(c1−c2)=1/cf 
It is required to make the feedback capacitor Cf programmable to accommodate for c1−c2 values that are usually in the range of a few fF to a few tens of fF. Furthermore, the feedback capacitor Cf is a small capacitor, for example 80 fF in 2 g mode (one g is the acceleration due to gravity at the Earth's surface). It is difficult to make such a small capacitor programmable and to have a fine grain size of programmability, for example, 1% of 80 fF. Since the feedback capacitor Cf is a floating capacitor, it is hard to manage the impact of the parasitic capacitance of switches used to implement the programmability. In addition, to accommodate a large acceleration input range of for instance 2 g, 4 g, 8 g and 16 g for the accelerometer 1, different programmable values of cf are required, for example 80 fF in the 2 g range mode, 160 fF in the 4 g range mode, 320 fF in the 8 g range mode and 640 fF in the 16 g range mode. It is very challenging to implement the feedback capacitor Cf to fulfil both programmability requirements for the grain size and range trimming simultaneously.
The patent application US 2015/0268284 A1 describes an apparatus and a method for interfacing an accelerometer (MEMS). The apparatus includes an interface circuit linked to a MEMS capacitor. The interface circuit includes an amplifier integrator connected at input to the MEMS capacitor through a switch. The output of the amplifier is connected to a comparator providing an output signal relative to the charge on capacitor MEMS. It is provided a feedback loop between the output of the comparator and the amplifier integrator, in which a feedback capacitor is provided for tuning also the gain of said apparatus. It is not provided to implement the feedback capacitor to fulfil both programmability requirements for the grain size and range trimming simultaneously, that it is a drawback.
The patent application US 2010/0231237 A1 describes an electronic circuit with a capacitive sensor for measuring a physical parameter. The sensor includes two capacitors mounted in differential, whose a common electrode is connected to one input of a charge transfer amplifier. An integrator is connected to the output of the charge transfer amplifier and is controlled by a dynamic comparator. Nothing is provided to implement a feedback capacitor to fulfil both programmability requirements for the grain size and range trimming simultaneously, that it is a drawback.
The patent application US 2015/0280668 A1 describes a capacitive programmable gain amplifier, but nothing is provided for tuning easily the grain size and range trimming simultaneously, that it is a drawback.